This invention relates to a phase-locked loop (PLL) for liquid crystal displays (LCDs) which generates a master clock signal, and more particularly to a phase frequency detection circuit and a method for detecting the phase frequency difference between an external synchronous signal and a horizontal synchronous signal from the PLL with accuracy.
In general, a conventional phase-locked loop (PLL) for generating a master clock signal MCLK for LCDs is shown in FIG. 6. In the conventional PLL, the phase frequency detector 100 compares the phase between an external synchronous signal Csa and a horizontal synchronous signal Hs from a horizontal synchronous signal generator 500 to generate a phase frequency difference signal PFD. A voltage controlled-oscillator 400 varies its oscillation frequency with the phase frequency difference signal PFD received from the phase frequency detector 100 through a low pass filter LPF 200 and a buffer 300 to generate a master clock signal MCLK. A horizontal synchronous signal generator 500 generates the horizontal synchronous signal Hs to the phase frequency detector 100 in accordance with the master clock signal MCLK. At this time, the external synchronous signal Csa which is externally provided to the phase frequency detector 100 is a signal where video signal, equalization pulse signal and vertical synchronous signal are removed from the composite synchronous signal by using a RC constant of a multivibrator.
The prior phase frequency detector 100 used in the PLL is comprised of a three-state buffer as shown in FIG. 4. The three-state buffer 90 of the prior phase frequency detector 100 is enabled in the low state period of the external synchronous signal Csa as shown in FIG. 5A to output the horizontal synchronous signal Hs as shown in FIG. 5B received from the horizontal synchronous signal generator 500 and is disabled in the high state period of the external synchronous signal Csa, thereby being high impedance. Accordingly, the three-state buffer 90 generates the phase frequency difference signal PFD as shown in FIG. 5C.
However, the prior phase frequency detector 100 compares the phase between the external synchronous signal Csa and the horizontal synchronous signal Hs to generate the phase frequency difference signal PFD only when the external synchronous signal Csa is in low state. Therefore, it is impracticable to detect the phase frequency difference between the external synchronous signal Csa and the horizontal synchronous signal Hs with accuracy, unless the horizontal synchronous signal Hs is overlapped with the external synchronous signal Csa of low state. In addition, if the period of the external synchronous signal Csa is different from that of the horizontal synchronous signal Hs, the phase frequency detector 100 detects the undesired phase frequency difference signal PFD.